00001 /* 00002 Copyright (c) 2002, 2003, Oliver Tscherwitschke 00003 All rights reserved. 00004 00005 Redistribution and use in source and binary forms, with or without 00006 modification, are permitted provided that the following conditions are met: 00007 00008 1. Redistributions of source code must retain the above copyright notice, 00009 this list of conditions and the following disclaimer. 00010 2. Redistributions in binary form must reproduce the above copyright notice, 00011 this list of conditions and the following disclaimer in the documentation 00012 and/or other materials provided with the distribution. 00013 3. The name of the author may not be used to endorse or promote products 00014 derived from this software without specific prior written permission. 00015 00016 THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED 00017 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00018 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO 00019 EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 00020 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 00021 PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 00022 OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 00023 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 00024 OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 00025 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00026 */ 00027 00041 #include <avr/io.h> 00042 #include <avr/interrupt.h> 00043 00044 #include "otos_cfg.h" 00045 #include "otos_def.h" 00046 #include "types.h" 00047 #include "hardware.h" 00048 00049 00061 #if defined __AVR_ATmega103__ 00062 /***************************************************************************** 00063 * ATmega103 00064 */ 00065 void otosInitHardware(void) 00066 { 00067 MCUCR = _BV(SRE); /* enable external RAM */ 00068 00069 #ifdef OTOS_BANKING 00070 DDRE = 0x3c; /* bit 2..5 for bank switching */ 00071 #endif 00072 00073 /* init timer 0 */ 00074 00075 #ifdef OTOS_DEBUG_RTC 00076 00077 TCCR0 = 00078 _BV(CS02) | /* prescaler 256 */ 00079 _BV(CS01) | /* prescaler 256 */ 00080 _BV(CTC0); /* clear on compare match */ 00081 00082 OCR0 = 91; /* set output compare register */ 00083 00084 #else 00085 00086 ASSR = _BV(AS0); /* use 32.768 Hz crystal */ 00087 TCCR0 = 00088 _BV(CS00) | /* prescaler 1 */ 00089 _BV(CTC0); /* clear on compare match */ 00090 00091 OCR0 = 127; /* set output compare register */ 00092 00093 #endif 00094 00095 TIMSK = _BV(OCIE0); /* enable output compare interrupt */ 00096 sei(); 00097 } 00098 00099 00100 #elif defined __AVR_ATmega128__ 00101 /***************************************************************************** 00102 * ATmega128 00103 */ 00104 void otosInitHardware(void) 00105 { 00106 00107 #ifdef OTOS_BANKING 00108 DDRE = 0x3c; /* bit 2..5 for bank switching */ 00109 #endif 00110 00111 /* init timer 0 */ 00112 00113 #ifdef OTOS_DEBUG_RTC 00114 00115 TCCR0 = 00116 _BV(CS2) | /* prescaler 256 */ 00117 _BV(CS1) | /* prescaler 256 */ 00118 _BV(WGM1); /* clear on compare match */ 00119 00120 OCR0 = 91; /* set output compare register */ 00121 00122 #else 00123 00124 ASSR = _BV(AS0); /* use 32.768 Hz crystal */ 00125 TCCR0 = 00126 _BV(CS0) | /* prescaler 1 */ 00127 _BV(WGM1); /* clear on compare match */ 00128 00129 OCR0 = 127; /* set output compare register */ 00130 00131 #endif 00132 00133 TIMSK = _BV(OCIE0); /* enable output compare interrupt */ 00134 sei(); 00135 } 00136 00137 00138 #elif (defined __AVR_ATmega163__) || (defined __AVR_ATmega323__) 00139 /***************************************************************************** 00140 * ATmega163 and ATmega323 00141 */ 00142 void otosInitHardware(void) 00143 { 00144 /* init timer 2 */ 00145 00146 #ifdef OTOS_DEBUG_RTC 00147 00148 TCCR2 = 00149 _BV(CS22) | /* prescaler 1 */ 00150 _BV(CS21) | /* prescaler 1 */ 00151 _BV(CTC2); /* clear on compare match */ 00152 00153 OCR2 = 91; /* set output compare register */ 00154 00155 #else 00156 00157 ASSR = _BV(AS2); /* use 32.768 Hz crystal */ 00158 TCCR2 = 00159 _BV(CS20) | /* prescaler 1 */ 00160 _BV(CTC2); /* clear on compare match */ 00161 00162 OCR2 = 127; /* set output compare register */ 00163 00164 #endif 00165 00166 TIMSK = _BV(OCIE2); /* enable output compare interrupt */ 00167 sei(); 00168 } 00169 00170 00171 #endif 00172